Integration of Hardware Efficient Algorithms
Integration av hårdvarueffektiva algoritmer

ETIN46, 7.5 credits, A (Second Cycle)

Valid for: 2025/26
Faculty: Faculty of Engineering LTH
Decided by: PLED E
Date of Decision: 2025-03-27
Effective: 2025-05-05

General Information

Depth of study relative to the degree requirements: Second cycle, in-depth level of the course cannot be classified
Elective for: D4-hs, E4-is, MSOC1
Language of instruction: The course will be given in English

Aim

The hardware realization of digital signal processing for machine learning, artificial intelligence, and massive continuous data streams is becoming increasingly important. Vertical optimisation techniques, from algorithms to a hardware level, will be constrained by performance as well as energy and hardware efficiency.

This course aims to provide students an understanding of how different implementation solutions affect properties like performance, flexibility, design time, and development cost.

The overall goal of the course is to teach a systematic approach to accelerating signal processing with focus on e.g, machine learning and wireless communication. The main part of the course provides students with an understanding of the design process for application-specific architectures based on an algorithm specification. This process should be carried out with a set of design constraints, including calculation capacity/throughput, power consumption, and silicon area.

Learning outcomes

Knowledge and understanding
For a passing grade the student must

• Gain an understanding of hardware acceleration for digital signal processing, as well as the relationship between architectural optimizations, power consumption, and silicon area.
• Being able to propose optimization strategies for machine learning and wireless communication topologies.
• Understand the effectiveness and richness of vertical optimisation strategies.

Competences and skills
For a passing grade the student must

• be able to develop a hardware accelerator architecture from a given set of criteria.
• be able to deploy a algorithm on a processor architecture and suggest alternative solutions

Judgement and approach
For a passing grade the student must

• have gained an overview of the field of implementation aspects of hardware acceleration.
• feel well equipped to design an application specific processor system given a specification using the methodologies covered in the course.

Contents

Digital signal processing is a highly expansive field which is a part of most modern electronic systems like mobile phones, smart devices, electrical vehicles etc.

These application often require real-time and low latency requirements at an attractive energy and silicon area cost.

This course will give insight into how an algorithm specification can be implemented from a given set of criteria. The main part of the course will be focused on the design of application specific architectures that can be implemented on either reconfigurable hardware, e.g. FPGAs, or as a custom circuit, i.e. ASIC.

Course content:

• Characterization and representation of signal processing algorithms: signal-flow, data-flow and dependence graphs.
• Quantization effects in algorithms for machine learning
• Architectural transformations – The concepts of retiming, pipelining and parallel processing for high throughput and/or low power consumption. Different types of architectures such as time-multiplexed and hardware mapped and how transformations can be made between them using the concepts of unfolding and folding.
• Algorithm transformations – How complexity in algorithms can be reduced and thereby reaching a more efficient implementation through the concept of strength reduction.
• Different numbering systems, how they are used and how they affect implementation and performance.
• Limitations of the current von Neuman architecture

Examination details

Grading scale: TH - (U, 3, 4, 5) - (Fail, Three, Four, Five)
Assessment:

The course consists of lectures and laboratory assignments. In order to pass the course 80% of the lectures need to be attended, and three small-scale projects need to get approved in time. Grade 4 and 5 will require 1 and 2 more projects, respectively. Projects will get approved by an oral examination and reports.

The examiner, in consultation with Disability Support Services, may deviate from the regular form of examination in order to provide a permanently disabled student with a form of examination equivalent to that of a student without a disability.

Modules
Code: 0125. Name: Laboratory Work.
Credits: 7.5. Grading scale: TH - (U, 3, 4, 5). Assessment: Approved projects and reports

Admission

Assumed prior knowledge: EITF75 Digital signal processing OR EITA50 Signal processing in multimedia OR EITF15/BMEF25 Digital signal processing - theory and applications OR BMEA05 Signals and systems OR EITG10 Systems, Signals and Discrete Transforms
The number of participants is limited to: No
Kursen överlappar följande kurser: ETI180 ETIN45

Reading list

Contact

Course coordinator: Joachim Rodrigues, joachim.rodrigues@eit.lth.se
Course homepage: https://www.eit.lth.se/course/etin45