Course syllabus


ETIN45, 7,5 credits, A (Second Cycle)

Valid for: 2023/24
Faculty: Faculty of Engineering, LTH
Decided by: PLED E
Date of Decision: 2023-04-11

General Information

Elective for: D4-hs, E4-is, MSOC1
Language of instruction: The course will be given in English


Digital signal processing is an area becoming increasingly more important in many products and systems of today. When algorithms within this area are to be implemented there is a large number of possible alternatives depending on varying requirements regarding for instance real time properties and power consumption. This course should give the students an understanding regarding how different implementation solutions affects properties like performance and flexibility and not least design time and development cost.

The overall goal of the course is to teach a systematic approach to the design process of digital signal processors. The main part of the course is focused on giving the students an understanding of the design process of application specific architectures given an algorithm specification. This process should be performed with a set of design constraints such as calculation capacity/throughput, power consumption and silicon area.

Learning outcomes

Knowledge and understanding
For a passing grade the student must

Competences and skills
For a passing grade the student must

Judgement and approach
For a passing grade the student must


Digital signal processing is a highly expansive field which is a part of most modern electronic systems. Examples of such systems are mobile communication, MP3/CD/DVD-players and medical systems exemplified by pacemakers and hearing aids and examples of algorithms are different types of filtering, coding and image recognition. Often a real time requirement exists, which limits the possibilities to perform the signal processing in a standard computer. Standard processors are one alternative which are developed to cover a wide range of applications and can therefore be used in many systems and gives high flexibility. However, many applications have requirements on for instance throughput and power consumption that demands application specific architectures.

This course will give insight into how an algorithm specification can be implemented from a given set of criteria. The main part of the course will be focused on the design of application specific architectures that can be implemented on either reconfigurable hardware, e.g. FPGAs, or as a custom circuit, i.e. ASIC. Standard signal processors and their relation to other solutions will also be discussed. The content is:


Examination details

Grading scale: TH - (U,3,4,5) - (Fail, Three, Four, Five)
Assessment: The course has three parts that when completed guarantees the grade 3: Homework assignments that are presented by the students during seminars, laboratory exercises and an assignment focused on dimensioning which will give a combined view of the different parts of the course. For a higher grade a written or oral exam is required.

The examiner, in consultation with Disability Support Services, may deviate from the regular form of examination in order to provide a permanently disabled student with a form of examination equivalent to that of a student without a disability.

Code: 0118. Name: Dimensioning Assignment.
Credits: 5. Grading scale: TH. Assessment: Approved Dimensioning Assignment
Code: 0218. Name: Home Assignments.
Credits: 1,5. Grading scale: UG. Assessment: Approved Home Assignments.
Code: 0318. Name: Laboratory Work.
Credits: 1. Grading scale: UG. Assessment: Approved Laboratory Work


Assumed prior knowledge: EITF75 Digital signal processing OR EITA50 Signal processing in multimedia OR EITF15/BMEF25 Digital signal processing - theory and applications OR BMEA05 Signals and systems OR EITG10 Systems, Signals and Discrete Transforms
The number of participants is limited to: No
The course overlaps following course/s: ETI180

Reading list

Contact and other information

Course coordinator: Joachim Rodrigues,
Course homepage: