Aim
Higher and eventually the system-on-chip integration will greatly improve the performance of an electronic system in speed, power, synchronization, cost, reliability and portability. With the highest density and lowest cost, CMOS is considered the main steam technology for system-on-chip design. In such a single chip system, the digital part will emit strong switching noise through different paths and seriously disturb the analogue part like sensitive receiver and A/D converter as well as digital circuit itself. Within the analogue part, strong transmitter and oscillator signals will also cause problems. The performance of such a chip will in a large extent depend on the design methodology capable of de-coupling different parts on the same chip. This course is intended to characterize these problems and to introduce corresponding design techniques.

Knowledge and understanding
For a passing grade the student must

• be able to describe the generation mechanism of digital switching noise in a CMOS chip,

• be able to describe noise coupling paths in the system-on-chip environment,

• be able to describe substrate noise propagation and substrate modelling,

• be able to describe basic techniques to reduce substrate noise,

• be able to describe low switching noise digital circuit design.

Skills and abilities
For a passing grade the student must

• be able to apply the knowledge acquired in the course to independently analyze the noise coupling and suggest the decoupling methods in a practical system-on-chip environment with the assistance of CAD simulation tools. This can be done in a group consisting of two students.

Judgement and approach
For a passing grade the student must

• be able to orally communicate the results obtained from the laboratory experiment and

• be able to contribute sufficient fundamental concept and knowledge so that a competent person in this area can document the idea, the problem and the solutions.

Contents
Trends of IC Technology, Chips and Packaging; Noise Coupling in System-on-Chip; Substrate Noise Characteristics and Propagation; Substrate Coupling Modelling: Substrate Biasing Strategy; Alternative Methods for Reducing Substrate Noise; Techniques for Experimental Study of Substrate Noise; Mechanisms and Effects of Switching Noise; Low Switching Noise Digital Design; Alternative Techniques for Reducing Switching Noise.

Literature
Aragonès X et al: Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs. Kluwer 1999. ISBN: 0-7923-8504-7.