Syllabus academic year 2008/2009
(Created 2008-07-17.)

Higher education credits: 4,5. Grading scale: UG. Level: A (Second level). Language of instruction: The course will be given in English. Compulsory for: MSOC1. Optional for: D3, E3, E3dps, F3, F3nfe. Course coordinator: Associate professor Pietro Andreani,, Inst för elektro- och informationsteknik. Prerequisites: EIT020 Design of Digital Circuits, ESS020 Analogue Electronics and ESS030 Physics of Devices. Assessment: Attending at least 8 lectures, finishing 3 laboratory works and delivering qualified lab reports guarantee pass with grade 3 (godkänd), without written examination. Home page:

Higher and eventually the system-on-chip integration will greatly improve the performance of an electronic system in speed, power, synchronization, cost, reliability and portability. With the highest density and lowest cost, CMOS is considered the main steam technology for system-on-chip design. In such a single chip system, the digital part will emit strong switching noise through different paths and seriously disturb the analogue part like sensitive receiver and A/D converter as well as digital circuit itself. Within the analogue part, strong transmitter and oscillator signals will also cause problems. The performance of such a chip will in a large extent depend on the design methodology capable of de-coupling different parts on the same chip. This course is intended to characterize these problems and to introduce corresponding design techniques.

Knowledge and understanding
For a passing grade the student must

Skills and abilities
For a passing grade the student must

Judgement and approach
For a passing grade the student must

Trends of IC Technology, Chips and Packaging; Noise Coupling in System-on-Chip; Substrate Noise Characteristics and Propagation; Substrate Coupling Modelling: Substrate Biasing Strategy; Alternative Methods for Reducing Substrate Noise; Techniques for Experimental Study of Substrate Noise; Mechanisms and Effects of Switching Noise; Low Switching Noise Digital Design; Alternative Techniques for Reducing Switching Noise.

Aragonès X et al: Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs. Kluwer 1999. ISBN: 0-7923-8504-7.